Conventional EPROM (Electrically Programmable Read Only Memory) transistors comprise layers for storing charges, i.e., electrons, which are usually called floating gates or stacked gates. EPROM transistors are programmable by adding electrons to the floating gate, thereby adjusting the threshold voltage (Vt), as from about 1.0 volt to greater than about 3 or above 4 volts. When the Vt is about 1, the EPROM transistor is considered unprogrammed (logic 0) or "blank." Thus, a blank EPROM transistor conducts current in normal circuit read out operations, while a programmed EPROM transistor (logic 1) does not conduct current. The existence of two logic states (1 and 0) in EPROM transistors enable binary data to be stored. EPROM transistors can normally be returned to an all blank (un-programmed) state by exposure to ultraviolet (UV) radiation of a certain wavelength and intensity, thereby effecting erasure. Conventional manufacturing techniques involve the production of wafers containing a plurality of EPROM circuits from which individual EPROM circuits are cut and packaged as by encapsulation. There are commercially available EPROM transistors encapsulated in hermetic packages with glass windows to enable UV erasure. There are also commercially available EPROM transistors encapsulated in a hard black plastic called OTP (One Time Programmable) devices which are not erasable with UV irradiation.
A UPROM (Unerasable Programmable Read Only Memory) cell differs from an EPROM in that it is not erasable by UV irradiation because it is covered by a metallization layer. Typical metals employed for the metallization layer include aluminum, silicon, e.g., polysilicon, copper and alloys thereof, preferably aluminum. See, for example, U.S. Pat. No. 5,063,424. In a typical semiconductor device comprising EPROM circuitry, UPROM transistors are located outside of the core array and connected to circuits which control the redundancy circuits and to a voltage supply.
A typical UPROM transistor is shown schematically in FIG. 1, wherein field oxide 2 is formed on semiconductor substrate 1 with an implanted insulation zone therebetween. Floating gate 7 is formed on substrate 1 with gate oxide 6 therebetween. Dielectric layer 8 is formed on floating gate 7 and polysilicon planarization barrier 9 formed on dielectric layer 8. Control gate line 13 is formed on polysilicon planarization barrier 9.
The current consumed by a semiconductor device is called the Icc current. There are several user modes for EPROM and UPROM transistors, including an active or dynamic mode and two sleep modes. A first sleep mode is called Icc standby (Iccsb) which is a standard TTL (Transistor Transistor Logic) conventional mode. The other sleep mode is Icc super-standby (Iccssb) which is a CMOS (Complimentary Metal on Silicon) conventional mode. The CMOS Iccssb mode is normally specified at a significantly lower current than the TTL Iccsb mode. For example, the TTL Iccsb mode may be specified at 0.001 amperes, while the CMOS Iccssb mode may be specified at 0.0001 amperes. In order to achieve such a low CMOS Iccssb mode, the threshold voltage of the EPROM and UPROM transistors is normally targeted at about 1-1.5 amperes, preferably 1-1.2 amperes, most preferably 1 ampere.
The CMOS Iccssb mode represents a major problem in the semiconductor industry. In most CMOS technologies, the Iccssb test failures represent a major source of rejects for data sheet parameters and, consequentially, considerable economic waste. The attainment of a CMOS Iccssb mode of 100 microamperes requires a basically defect free manufacturing process.
The problem of CMOS Iccssb test failures is exacerbated by the existence of numerous possible sources of such failures. The most common sources of such failures are suspected to be defects generated during the various manufacturing processes of the semiconductor circuitry. Semiconductor processing comprises hundreds of steps. In order to isolate the particular step or combination of steps which create MOS Iccssb test failures, a complex failure analysis must be performed by highly skilled individuals. The success of a failure analysis project is highly dependent upon the skills and resourcefulness of the individuals conducting the failure analysis.
Semiconductor devices comprising EPROM and UPROM transistors are subject to an increasingly high CMOS Iccssb failure rate. Failure rates of about 75-88% are not uncommon. It was originally thought that the majority of such failures stemmed from a leakage current due to the short channel lengths of the transistors. However, upon extensive investigation and experimentation, we discovered that the source of most CMOS Iccssb mode failures stemmed from the UPROM redundancy circuit. Upon micro-probe analysis, it was further discovered that UPROM transistors were turning on during the CMOS Iccssb mode, thereby generating failures. We attributed this problem to a negative threshold voltage which, in effect, turned the UPROM transistor into a depletion transistor. Upon further investigation, it was confirmed that the failed devices contained UPROM transistors having negative threshold voltages, with negative threshold voltages of about -0.3 and -0.4 volts not uncommon. Thus, during the MOS Iccssb mode conducted at 0 voltage, a UPROM transistor having a negative threshold voltage would turn on, thereby resulting in an inspection failure.
Upon extensive investigation, we discovered that the source of the negative threshold voltage problem is charge trapping during fabrication, i.e., injection of electrons into the floating gate of the UPROM transistor during charging. Several experimental attempts to correct the threshold voltage of the UPROM transistors met with failure and the yield continued to run between 12% and 25%. The experimental attempts failed primarily because UPROM transistors, unlike EPROM transistors, cannot be erased with ultraviolet radiation.